Front end VLSI design can’t get easier than this
Do you want to build just verilog models or high-quality verilog models in half the time?
Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?
How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform
This webinar is really important for people who have taken up my RISC-V ISA course on Udemy, as we will show efficient RTL implementation of some instructions in this one.
Enjoy the webinar and Happy Learning....
Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform
Build their own verilog models for IP's using a simpler and powerful Verilog design environment
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Tips on order in which you need to learn VLSI and become a CHAMPION:If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.Then, as you all...
Steve Hoover is the founder of the Massachusetts startup, Redwood EDA. Steve holds a BS in electrical engineering, summa cum laude, from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has extensive expertise in high-performance server CPU design, having contributed to multiple generations of Alpha microprocessors at DEC and Compaq as well as...
Casualmente buscando información en github acerca de RISC-V encontré una implementación en FPGA realizada en TL-Verilog ¿? Haciendo un poco de busqueda en internet encuentro un curso en EDX al cual me apunto (gratis) para entender un poco este lenguaje. Poco después, siendo usuario antiguo de udemy veo que también hay un curso (webminar) a un precio razonable y decido comprarlo. Lo he terminado y me ha parecido muy interesante pero me queda mucho trabajo por hacer y por aprender. Un gran viaje empieza con un simple paso. Gracias por el curso.
Poor audio!
I thoroughly enjoyed the course and learned lot about TL Verilog.
Right now it was just introduction which was very smoothly done.
not about RISC-V
nice stuff, good for beginners
TL-Verilog is definitely revolutionary, the way it has been designed is good enough to put it into good use right now, and integrate with existing Verilog based designs. And an even more interesting fact is that it is still evolving and expanding to other HDLs such as VHDL!
No idea why they titled the course as 'Pipelining RISC-V'. This course is not about pipelining RISC-V at all. It could be any design block. It is mostly about TL-verilog and makerchip.com.
Clear and concise presentation of the subjects.
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Nguyen L.
It's mostly review for me since I have designing/verifying ASIC for decades now. I want to teach my son TL-Verilog.