VSD - Static Timing Analysis - I

Brief Summary

This course is all about essential timing checks in VLSI. It delves into static timing analysis, signoff timing, and helps you get familiar with key terminologies and practices used in the industry. You'll be all set to avoid those annoying timing violations.

About This Course

VLSI - Essential timing checks

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

• Understand various STA checks for timing closure

• Able to do a quality analysis for real designs

• Know-how on how real STA works in industries, something which you will not find in any books